This invention relates to electrical inverters and more particularly to circuits for controlling power pole switching in pulse width modulated inverters.
Pulse width modulated D.C. to A.C. inverters approximate sine-wave outputs by switching power pole switches at a rate higher than the fundamental sine-wave frequency. In the design of pulse width modulated D.C. to A.C. inverters, it is desirable to switch the power stage in a manner which reduces certain harmonics to low values so as to ease the burden of filtering the output power to obtain a sinusoidal voltage wave. Fairly small errors in switching times can produce harmonic voltages many times greater than desired. This usually results in the circuit filter being made considerably larger than theoretically necessary to suppress these harmonics.
In a transistor inverter, for example, it is necessary to provide an underlap condition to prevent shoot-through during the switching operation. This means that to switch an output point from one polarity to another, there must be a delay after the conducting transistor is turned off, to be sure it is no longer conducting, before the other transistor is turned on. Many times load conditions are such that the second transistor does not conduct at all since load current is shunted through a commutating diode, thereby shortening the switching time to that of the transistor turn-off time. Thus the switching time is quite variable depending on the instantaneous load current as well as the transistor turn-off characteristic. Therefore, the prescribed switching schedule is not met, resulting in unpredicted harmonics.
The present invention minimizes output distortion due to switching errors by predicting the switching time required for each switching point and using this prediction to adjust the starting time for each switching period so that switching is accomplished on schedule. In general a reference waveform which is to be reproduced at the power pole output will be available to the switching control circuitry. Pulses within the reference wave are to be reproduced at the power pole output after a preselected time interval.
This delayed switching schedule is accomplished by measuring the power pole switching time for a given pulse in an output cycle and subtracting the measured switching time from the preselected time interval to obtain a delay time. The switching period for the corresponding pulse in the succeeding output cycle is then initiated at a point equal to the delay time, as obtained from the previous cycle, following the appropriate reference waveform pulse. This process is repeated for each power pole output pulse. During steady state operation, it is reasonable to expect that switching periods will be the same length at corresponding switching points in each subsequent cycle. Therefore, the power pole will switch after a preselected time interval following the reference wave pulses.
A control circuit constructed in accordance with this invention includes means for measuring switching time, means for determining the difference between a preselected time interval and the measured switching time to obtain a delay time, and means for initiating the power pole switching sequence for the corresponding pulse in the succeeding output cycle after the delay time following an appropriate pulse in the reference waveform. By appropriately timing the switching function, multiple phase inverters can be controlled by a single control circuit.
D.C. content of the inverter output is controlled by sensing D.C. content, generating a compensation signal, and varying pulse width of the output pulses in response to the compensation signal. A circuit which accomplishes this compensation includes an integrator which senses D.C. content of the output and produces a compensation signal and a comparator which compares the compensation signal to the power pole output voltage which has been reduced by a voltage divider and modified to have controlled rise and fall times. The comparator then produces a signal representing the phase voltage modified in pulse width depending on D.C. content. When the modified phase voltage signal is fed back to the firing control circuit, the firing circuit alters the power pulse width to eliminate the D.C. component of the output.